********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Mar 24, 2014
*ECN S14-0599, Rev. A
*File Name: Si8424CDB_PS.txt and Si8424CDB_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8424CDB D G S 
M1 3 GX S S NMOS W= 1779956u L= 0.25u 
M2 S GX S D PMOS W= 1779956u L= 0.36u 
R1 D 3 1.247e-02 TC=2.534e-03, -3.230e-07 
CGS GX S 1.220e-09 
CGD GX D 8.277e-11 
RG G GY 3.5 
RTCV 100 S 1e6 TC=2.040e-04, 2.727e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 1779956u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.3e-8 
+ RS = 0 KP = 2.072e-05 NSUB = 1.709e+17 
+ KAPPA = 6.296e-02 NFS = 3.85e+11 
+ LD = 0 IS = 0 TPG = 1 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.3e-8 
+NSUB = 3.574e+17 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 T_MEASURED = 25 BV = 9 
+RS = 6.549e-02 N = 9.988e-01 IS = 1.265e-09 
+EG = 1.064e+00 XTI = -9.167e+00 TRS1 = 2.086e-03 
+CJO = 2.992e-10 VJ = 1.466e+00 M = 5.376e-01 ) 
.ENDS 
